1. Field of the Invention
The present invention relates to an analog layout migration methodology for quickly providing multiple layouts for integrated circuit (IC), and more particularly, to a method for providing analog layout results with different aspect ratios while keeping similar or better circuit performance of the original layout.
2. Description of the Prior Art
In modern integrated circuit (IC) industry, analog ICs become more and more important. An analog IC is described by a netlist which includes a set of interconnected device modules such as transistors, capacitors, resisters and other devices. The functionality and performance of the analog ICs are heavily influenced by the placement of the device modules of the circuits. A system-on-a-chip (SOC) design which integrates digital and analog circuits has revolutionized the semiconductor industry. As new process technologies scale to smaller sizes, when a design is retargeted to the new process, reusing an existing layout as much as possible instead of redesigning a new one from the scratch becomes important to meet aggressive time-to-market schedules.
In digital circuits, advancement in the computer-aided-design (CAD) tools and the cell-based methodology made significant progress for optimum reuse of existing digital design. On the contrary, CAD tools in analog circuits still require much manual intervention. Since analog performance is strongly sensitive to mismatches due to process variations, operating conditions and parasitics, some constraints (e.g., symmetry, building blocks) need to be satisfied for alleviating these effects. In most cases, analog designers rely on their past experience and expertise to achieve desired performance by manually redrawing layouts when a circuit migrates to the new process or retargets to a new specification. Such process is quite time consuming and tedious. Therefore, a methodology that can automatically incorporate designer's knowledge into layout migration process will be important to reduce the design and turn-around time.
On the other hand, in order to allow analog designers to utilize electronic design automation (EDA) tools more efficiently, process design kit (PDK) gradually plays an important role in the analog circuit design. Schematics are constructed by PDK symbols, and layouts will be composed of Parametric Cells (Pcells) of corresponding devices in the PDK. According to different parameters (e.g., width, length, finger number, etc.) of each device, Pcells can help generate layout instances with clean design-rule check for all devices. Hierarchical relationship between devices and layout construction will be easier to keep and modify in the future.
Several approaches reported in the literature have focused on this issue. As a circuit is retargeted to a new technology or new specification, additional considerations should be addressed as well. The new result with exactly the same topology may not be the desired placement in the migrated technology because of the layout dimension or the layout area. Most of the layout-migration algorithms are based on layout compaction, since it closely resembles the source layout and automatically constructs a symbolic structural template to preserve layout topology, design rules, symmetry and matching information from an existing layout. The new device sizes will be imposed on the template during migration. Then this template can be solved by the set of constraints with linear programming (LP) or graph based algorithm to minimize layout area. The number of constraints and variables with LP affects the total runtime of layout migration. As layout becomes complicated, it becomes very time-consuming.
As a result, layout compaction is not a good approach since it just shrinks the chip size according to new device dimensions without considering any other optimized layout solutions. In addition, layout compaction does not provide sufficient flexibility for designers to modify layouts for other objectives as well.
Therefore, what is needed is a systematic approach to migrate an existing layout to a new technology to generate optimized layouts for the new technology while satisfying all the constraints.